The invention relates generally to an SRAM circuitry for storing at least one data word, and more specifically to a global bit line restore of an SRAM circuitry, as well as to a method for restoring of a global bit line in an SRAM circuitry.
Today, computing systems require even more and faster memory chips. The chips could be main memory chips, as replacement for bulk memory in the form of solid state random access memory (RAM) for on-chip memory elements that are integrated with central processing unit (CPU) elements. CPUs today comprise typically level-1 (L1 cache) and level-2 (L2) caches. Main memory in computer systems is typically realized by dynamic RAM elements. Such elements need a regular refresh of the stored content and are comparably slow in contrast to static RAMs (SRAMs). SRAMs are not required to be refreshed regularly to keep their content. They keep the information stored as long as an SRAM cell is supplied with electrical power.
Memory elements that are very close to the CPU or algorithmic logical unit (ALU), e.g. L1 or L2 cache, are sometimes used for address translation purposes. Such memory elements have to be extremely fast in order to keep pace with ever decreasing clock cycles of the CPU. These memory elements are typically made of SRAM cells. A group of SRAM cells may build a memory word comprising data bits that may be addressed individually together as a data word. The addressing may be done by decoding coded address lines that form an individual word line (WL). The word line may represent a sort of select line for a select signal for one or more of the individual memory cells, e.g., a memory word. The memory cells may be realized by typical SRAM cells with six transistors as they are well known in the art. A word may be typically eight bits long. It may as well have just one bit length or 64 bit length or any other length of bits.
When an SRAM cell is selected by a word line, the stored content in form of a bit will be available at an output line of the SRAM cell. This information may be a “0” or a “1” signal. In order to make the stored information available to other components of a computer system, the output lines of several SRAM cells belonging to different data words are coupled to a local bit line (LBL). If an SRAM cell is selected by a signal on the associated word line, the stored signal (e.g., “0” or “1”) is available on the local bit line and may be detected as a voltage on the local bit lines.
One drawback of a conventional SRAM device is that the discharge of the local bit line may be delayed due to RC effects induced by distant connection routes between elements in an SRAM circuitry, e.g., by different metallization levels. As a result, the performance or speed of a conventional SRAM device may be less than ideal. Therefore, in order to guarantee a reliable read-out of cells at high speed, a special read-out procedure is followed.
This procedure includes “charging” or “pre-charging” of a local bit line with electrical charge carriers before reading or evaluating information out of an SRAM cell, i.e., before detecting voltages on the local bit line. This process may be called “restore” of the local bit line. It should not be intermixed with a refresh or refresh cycles required for dynamic or DRAM cells. Before detecting voltages at a local bit line, the local bit line is charged with charge carriers. The charging is stopped just before a coupling or connection is established between the SRAM cell and the local bit line. If the content in the SRAM cell is “0” the local bit line may be discharged through the SRAM cell and a logical value “0” may be detected on the local bit line. If on the other hand, the content of the SRAM cell is “1”, then no discharge of the carriers of the local bit line happens and a logical “1” is detected on the local bit line.
It may be important to control the timing between a restore and voltage detection/reading of the local bit line very carefully. Firstly, the restore window may be as large as possible to charge the local bit line as much as possible. On the other hand, there may not be an overlap with the “select” of the SRAM cell by the word line and the connection between the SRAM cell and the local bit line because this may result in a short cut or unwanted power burns. As an example, document U.S. Pat. No. 7,170,774 B2 discloses a global bit line restore based on a clock signal.
A concept of bit line segments in a memory array is disclosed by U.S. Patent Publication No. 2009/0231898 A1. The embodiments of this document are discussed in the context of dynamic memory cells.
Document U.S. Patent Publication No. 2005/0007861 A1 discloses an SRAM cell design directed to low power consumption, if the SRAM is in a stand-by mode. Surrounding elements that are not required to keep the information in a memory cell are powered down.
Such a time management of different select, read, and restore signals becomes critical as the frequency of processors constantly increases. The luxury of time margins between associated signals is thereby reduced. This applies especially to cases in which a system frequency approaches 5 Ghz or more.
The local bit line design, as just described, is also known as shared distributed dynamic node. Because of RC effects and other physical requirements, today, a number of local bit lines may be coupled or connected to a global bit line. In this case, a number of SRAM cells may be coupled to corresponding local bit lines. SRAM cells may not be coupled to global bit lines directly. However, a number of local bit lines may be coupled to a global bit line. The reading from the global bit line is done in a similar manner as just described in case of the local bit lines.
Prior to a voltage detection/read, the global bit line may be charged. However, the timing for the charging or restore of the global bit line may be even more time critical and may need to be synchronized very effectively with a select signal for triggering a read of a data bit of an SRAM cell.
A known technique to control the restore of the global bit line may be based on a clock signal. However, the high frequencies with which today's CPUs are operated imply that timing inaccuracies cannot be avoided in order to generate an optimal global bit line restore signal. For example, timing control variations of word clock signals may increase a misalignment of a local and a global restore (short expression for local bit line restore or global bit line restore).
In addition, there are dependencies to be taken into account. Local and global restores have a strong relationship that needs to be honored in order to prevent unnecessary power burn: a) global restore may only start after local restore is started; b) a next read cycle—or evaluation cycle—may only start after the global bit line restore may have been finished. Prior art suffers to guarantee an advanced timing due to a completely separate path for a global bit line restore compared to a local bit line restore. In particular, if hardware process variations are involved, timing variations for a global bit line restore may be involved, since no common path exists between local and global bit line restore signals generation. It may also be mentioned that—in prior art technique—a timing control variation of a word clock may increase a misalignment of a local and a global bit line restore.
Therefore, there is a need for an architecture or topology for effective coordination of a local and a global restore procedure.